As the storage capacity of an integrated circuit (IC) memory is increased from one generation to the next, the sizes of memory arrays increase, as measured in terms of the row and column space of the array, i.e., the number of wordlines of the memory array, as multiplied by the number of bitlines of the memory array. Memory arrays having larger numbers of wordlines and bitlines generally have less overhead in form of support circuitry for accessing the arrays, as a percentage of the total IC area occupied by the memory. Support circuitry including row decoders, wordline drivers, column decoders, first sense amplifiers and second sense amplifiers, etc. must be provided for every memory array on the IC. However, such support circuitry takes up a significant amount of IC area that cannot be used for the storage of data. To increase the utilization efficiency of IC area, it is therefore advantageous to increase the numbers of wordlines and bitlines of each memory array relative to the numbers of circuits provided therein for support of the memory array.
In a conventional dynamic random access memory (DRAM), it is evident that a single memory array cannot have a row space including an arbitrary number of wordlines that is served by a single set of the same bitlines, because the bitlines which span the row space would have very large capacitance, such that the charge stored on a capacitor of a storage cell coupled to the bitline would appear as an extremely small signal, making it difficult to read the storage cell. In addition, the large capacitance of the bitline has an RC time constant which inhibits the speed of accessing cells of the memory array. Even at the scale of integration density in today's leading DRAM technology, bitline capacitance can be, for example, 200 fF, which significantly exceeds the capacitance of a storage cell within the DRAM, which is, for example, 30 fF, such that bitline capacitance may soon become a limiting factor in the design of DRAMs.
FIG. 1A illustrates schematically, in plan view, a memory cell array of a dynamic random access memory (DRAM). As shown in FIG. 1A, a memory cell array 10 of a DRAM includes a plurality of storage cells 12, each including a capacitor 11 for storing a charge representing a data bit, and an access transistor 13 for controlling the transfer of the charge representing the data bit to and from the capacitor 11 of the storage cell 12. A plurality of substantially parallel wordlines 14 and 15 are provided for operating the access transistors 13. A plurality of substantially parallel bitlines 16 and 17 are also provided in a direction transverse to the wordlines, each coupled to storage cells 12 of the array 10 and sense amplifiers 18 for transferring a data bit signal therebetween.
In a typical read operation, a wordline 14 is activated by raising the voltage thereon to turn on transistors 13 that have gates coupled to the wordline 14, such that the charges stored on capacitors 11 of storage cells 12 connected to those transistors 13 is transferred to corresponding ones of the bitlines 16. On each bitline 16, therefore, a data bit signal corresponding to the change in one accessed storage cell is transferred to a corresponding sense amplifier 18. As shown in FIG. 1B, when a particular wordline 121 is active, a sense amplifier 118 connected thereto amplifies a small voltage difference signal between the bitline 116 that is currently accessed and a non-accessed bitline 117 to full high and low logic levels, thereby determining the value of the data bit read from a storage cell 112 coupled thereto. Writeback is then usually performed from the sense amplifier 118 to the storage cell 112, because when the data bit signal is read, the charge stored on the storage capacitor 111 is transferred to the bitline 116 and consequently no longer exists in storage capacitor 111. When a wordline 121 is activated, a bitline 116 is accessed, while bitline 117 acts only as a reference input to sense amplifier 118. This arrangement assures that noise that may be present on both the bitline 116 and the reference bitline 117 cancel each other out in sense amplifier 118. On the other hand, when a different wordline 122 is activated, a storage cell 119 on a bitline 117 is accessed, while bitline 116 acts only as a reference input to the sense amplifier 118. When bitline 116 and reference bitline 117 are located adjacent to each other in the same array, as described here, this is known as folded bitline sensing.
A typical write operation begins by first reading the storage cell 112 that is to be written. This is performed by activating a wordline 121, which turns on transistor 113 of the storage cell 112. This has the effect of clearing the data bit stored before that time from the storage cell 112 by transferring the charge stored in capacitor 111 to the bitline 116. A signal representing the data bit stored in the storage cell 112 coupled to the wordline 121 is then transferred on the bitline 116 to the sense amplifier 118 where the signal is then amplified to a high or a low logic level. Thereafter, a data bit is written to a selected storage cell 112 that is accessed by the active wordline 121, while remaining storage cells 112 (not shown) accessed by the activated wordline 121 are written back from other sense amplifiers (not shown) with the data that they stored prior to being read. This is known as a read modified write operation, as the writing of a selected storage cell 112 accompanies the reading and restoring of data to other storage cells (not shown) which are accessed by the same activated wordline 121.
FIG. 2A schematically illustrates the configuration of a storage cell 12 of a memory array 10, in relation to which an embodiment of the invention is provided. The storage cell comprises a storage capacitor 22 having one plate tied to a reference voltage (typically ground as shown in FIG. 2A or half of the bitline high voltage) and having its other plate tied to the sources of access transistors 24. The access transistors 24 are coupled in parallel, having drains tied to bitline 16 and gates tied to wordline 14. With reference to FIG. 2B, as described in greater detail below, storage capacitor 22 is formed within a deep trench 20, and the sources and conduction channels of access transistors 24 are formed along sidewalls of an upper region of the deep trench 20 above the storage capacitor 22. Additionally, the gates of the access transistors are formed within the upper region of deep trench 20, above the trench top oxide (TTO) 32. An advantage of the arrangement shown in FIG. 2A is that the drains 38 of access transistors 24 are formed on both sides of deep trench 20, which provides the equivalent of twice the channel width of other transistors having comparable gate lengths.
FIG. 2B illustrates an array of storage cells 12, which is described in commonly assigned published U.S. Patent Application Publication No. US 2002/0196651 A1 and is background to the present invention, but which is not admitted to be prior art. The illustrated cross section is shown in the direction of a bitline 16. As shown in FIG. 2B, storage capacitor 22 is formed within the deep trench 20 etched into a single crystal semiconductor of a substrate 26. Deep trench 20 also comprises a heavily doped buried strap regions 28, which provides source regions (hereinafter, “source”) for access transistors 24. Each of the buried strap source regions 28 are electrically connected to the node electrode 21 formed within the lower region of the deep trench 20, thus forming the connection between access transistors 24 and the storage capacitor 22. Deep trench 20 also includes trench collar oxide 30 and trench top oxide 32, which prevent parasitic current leakages.
In addition to the buried strap source region 28, each access transistor 24 also includes doped gate polysilicon (hereinafter, “poly”) 34, formed within the upper region of deep trench 20 and gate oxide 36. Note that gate oxide 36 is formed on sidewalls of the upper region of the trench 20 and is contacted by gate poly 34. As further shown in FIG. 2B, the gate poly 34 is contacted by an active wordline 14. Each access transistor 24 further includes a drain region 38 located near the top surface of the single-crystal semiconductor of the substrate. Each drain region 38 is connected to the bitline 16 via bitline contacts 23.
Note that other wordlines 15 are shown in FIG. 2B. These wordlines are connected to other storage cells, but not the storage cells being illustrated in FIG. 2B. As such, those wordlines 15 are referred to as passing wordlines as per FIG. 2B, whereas the wordline 14 contacting gate poly 34 is referred to as an active wordline. In an exemplary embodiment, wordlines 14 and 15 include a low resistive conductor layer formed on an optional barrier layer over heavily doped polysilicon. For example, the wordline may be formed as a dual layer conductor including layers of polysilicon and tungsten nitride 40, over which is formed a tungsten or tungsten silicide (WSi) layer 42. The conductive layers are surrounded by a nitride insulating layer 44 to insulate the wordlines from bitline contacts 23 and the bitline 16. Additionally, gate poly 34 is insulated from adjacent features, such as doped regions 38, by an insulating spacer 46 and insulating cap 48. Spacer 46 is preferably formed of an oxide layer and cap 48 is preferably formed of a nitride. Other materials could be substituted depending upon the process flow, provided adequate isolation is provided to gate poly 34. The passing wordline 15 is insulated from the doped regions 38 by an array top oxide (ATO) 39.
As shown in FIG. 2B, each storage cell 12 includes two access transistors 24. Each access transistor 24 shares a common gate poly 34, but there are two gate oxides 36, two sources 28, and two drains 38. Each drain region 38 of each transistor has two contacts 23 to the bitline 16. Each transistor 24 further shares a common drain region 38 with a neighboring transistor.
In view of the foregoing, it would be desirable to reduce the length of bitlines of a memory array, such that capacitance of the bitlines are reduced, thereby permitting bitline signals to be distinguished, while keeping the access time of the memory array within target.
It would further be desirable to multiplex signals of bitlines having reduced length onto a master bitline by transistors of an array of transistors of a memory array.
It would further be desirable to provide a plurality of transistors used for multiplexing bitline signals on to a master bitline within the same well within which transistors of an array of transistors of a memory are provided.